In semiconductor memory devices, such as a Dynamic Random Access Memory (DRAM) device, the memory cell is typically made up of two main components, a field effect transistor (FET) and a storage capacitor. The FET is typically a standard transistor structure having a gate electrode overlying a channel region with the channel region spanning between the source and drain electrode. In order to obtain smaller memory cell scaling, the vertical sidewall gated transistor structure in conjunction with the storage capacitor has evolved.
The DRAM memory cell was also fabricated using semiconductor-on-insulator or silicon-on-insulator (SOI) substrates to help reduce soft errors and improve refresh times that the typical DRAM substrate may be prone to. SOI substrates typically comprise a thin layer of active semiconductor, such as silicon, on an underlying insulating layer, such as silicon dioxide (SiO2) and the SOI fabrication technology is well known to one skilled in the art and is often referred to as silicon-on-insulator.
U.S. Pat. No. 5,448,513 discloses a capacitorless DRAM fabricated on a silicon-on-insulator (SOI) substrate. Some of the advantages gained by forming a capacitorless DRAM and utilizing an SOI substrate include reducing soft-error rate that are inherent in “gain cell” memory devices, a less complex fabrication process and a smaller memory cell that allows dense memory scaling. However, current lithographic capabilities provide new challenges to fabricate DRAM memory cells that are scalable to the minimum lithographic line feature.
What is needed is a transistor structure that is scalable to a minimum lithographic feature size for use in semiconductor memory devices, such as for a capacitorless DRAM device, a Flash memory device or an embedded memory device.